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Description
In this paper, a display system with a foveated rendering is proposed to reduce a high data rate for virtual reality (VR) applications. The proposed display system implements an encoding logic and a decoding logic in FPGA and ASIC with OLED-on-silicon (OLEDoS) microdisplay, respectively, by employing the proposed data protocol based on the focal point. A visual field map for the encoding logic in FPGA also enables an efficient real-time operation with respect to merged features and the focal point. The image demonstration of the proposed system showed a successful implementation of the display system for a resolution of 3,000 x 2,720 with 3,500 ppi and 90 Hz frame rate. Moreover, the system demonstrates the achievement of a data compression up to 90% and a 75% reduction of the power consumption for the interface. Therefore, the proposed display system is a proper solution to construct the highly immersive and real-time VR system.
References
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[2] Y. Onoyama, J. Yamashita, H. Kitagawa, E. Hasegawa, A. Makita, S. Yokoyama, R. Asaki, E. Kambe, T. Nishimura, J. Yamada, K. Uchino, S. Makimura, Y. Shiraishi and T. Urabe, “0.5-inch XGA Micro-OLED Display on a Silicon Backplane with High-Definition
Technologies,” in SID Symp. Dig. of Technical Papers, vol. 43, pp. 950-953, 2012.
[3]Anjul Patney, "Perceptual insights into foveated virtual reality.," In Proceedings of the NVIDIA GPU Technology Conference 2017 Talks.
| Keywords | virtual reality, display driver IC, foveated rendering, data compression, OLED-on-silicon |
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