Speaker
Description
Artificial intelligence (AI) brings about significant advancements in various research areas such as visual perception, natural language processing, and autonomous vehicles. The traditional von Neumann computing architecture, which separates processing and memory units, is facing limitations due to the increasing data transfer requirements in AI applications. The fundamental operations of artificial intelligence (AI) implemented with embedded neural networks consist of multiply-accumulate (MAC) operations [1]. However, performing high-capacity MAC operations in a small space while maintaining energy efficiency remains a challenge. Processing-in-Memory (PIM) integrating memory and processing elements allows calculations to be performed at the same location without the need for data movement and improves the energy efficiency of memory-based computing systems by minimizing data movement and reducing latency [2]. PIM computing system based on resistive random-access memory (ReRAM) crossbar arrays (CBA) can be reconfigurable and potentially perform parallel and general computing tasks [3]. The use of ReRAM-based PIM is increasingly attractive for energy-efficient accelerators in edge computing, where primary power sources are batteries or energy-harvesting devices. Specifically, edge computing devices have limited data processing needs and spend most of their time in standby mode. Compared to other non-volatile memories, moreover, ReRAM CBA has the advantage of achieving high capacity since the structure can be implemented as a three-dimensional memory, allowing for the minimization of the unit cell area to 4F^2 and the stacking of multiple layers [4]. This makes ReRAM-based PIM with moderate performance a favorable option for edge computing. However, a challenge in the crossbar structure is the presence of sneak currents that can occur from neighboring cells [5]. A self-rectifying ReRAM (SR-ReRAM) resolves the sneak leakage problem and reduces the power consumption in the CBA [6]. This paper proposes a circuit-compatible model that mimics the physical operations of the SR-ReRAM. The model is based on the behavior of voltage-controlled, bipolar memristors that exhibit diode-like rectification behavior when reverse-biased. The embedded bias scheme is also proposed for the SR-ReRAM CBA to reduce the sneak current more and improve CBA current read margin. The proposed compact model is implemented in Verilog-A and shows a DC operation error of 1.25% and an AC operation error of 2.43% at the read operation voltage. The SR-ReRAM has an asymmetric I-V characteristic and effectively blocks the sneak current flowing from bit line to word line. The embedded bias applies different voltages to the selected and unselected cells and reduces the sneak current by 1/200 compared to SR-ReRAM-only CBA.
References
[1] V. Camus, L. Mei, C. Enz, and M. Verhelst, “Review and benchmarking of precision-scalable multiply-accumulate unit architectures for em bedded neural-network processing,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 9, no. 4, pp. 697–711, 2019.
[2] P. Chi et al., “Prime: A novel processing-in-memory architecture for neural network computation in ReRAM-based main memory,” ACM SIGARCH Comput. Archit. News, vol. 44, no. 3, pp. 27–39, 2016.
[3] Q. Xia and J. J. Yang, “Memristive crossbar arrays for brain-inspired computing,” Nature Mater., vol. 18, no. 4, pp. 309–323, Apr. 2019.
[4] Y. Chen, “ReRAM: History, status, and future,” IEEE Trans. Electron Devices, vol. 67, no. 4, pp. 1420–1433, 2020.
[5] Y. Li, W. Chen, W. Lu, and R. Jha, “Read challenges in crossbar memories with nanoscale bidirectional diodes and ReRAM devices,” IEEE Trans. Nanotechnol., vol. 14, no. 3, pp. 444–451, May 2015.
[6] K. Jeon et al., “Self-rectifying resistive memory in passive crossbar arrays,” Nature Commun., vol. 12, no. 1, p. 2968, May 2021.
| Keywords | artificial intelligence, deep neural network, crossbar array, compact model, self-rectifying ReRAM, sneak current |
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